Mechanical stresses are known to play a role in charge carrier mobility which affects Voltage threshold shifts. The effect of induced mechanical stresses, also referred to as strain in MOSFET device channel regions, on charge carrier mobility is believed to be influenced by complex physical processes related to acoustic and optical phonon scattering.
Generally, manufacturing processes are known to introduce stress into the MOSFET device channel region. For example, stress is typically introduced into the channel region by formation of an overlying polysilicon gate structure and silicide formation processes. In addition, ion implatation and annealing processes following formation of the gate structure typically introduce additional stresses into the polysilicon gate structure which are translated into the underlying channel region altering device performance.
Prior art processes have attempted to introduce offsetting stresses into the channel region by forming stressed dielectric layers over the polysilicon gate structure following a silicide formation process. These approaches have met with limited success, however, since the formation of the stressed dielectric layer typically has a degrading electrical performance effect, for example drive current, on a CMOS device formed to operate on the opposite type of majority charge carrier (e.g., N vs. P charge carrier). For example, as NMOS device performance is improved, PNMOS device performance is degraded.
Other shortcomings in prior art approaches are the adverse affect of the dielectric stress altering layer on subsequent gap filling ability of a subsequent inter-layer dielectric (ILD) layer deposition. For example, the thickness of the dielectric stress layer, and therefore stress altering influence, is limited due to the formation of narrower gaps between devices, a limitation that will increase as device sizes and gap sizes between devices decreases.
These and other shortcomings demonstrate a need in the semiconductor device integrated circuit manufacturing art for improved CMOS device manufacturing methods to control a mechanical stress level in CMOS device channel regions to improve device performance and reliability.
It is therefore an object of the present invention to provide improved CMOS device manufacturing methods to control a mechanical stress level in CMOS device channel regions to improve device performance and reliability, in addition to overcoming other shortcomings of the prior art.